Worst Case Switching Pattern for Core Noise Analysis (PDF)

This paper demonstrates an optimum methodology to capture the worst case switching activity when performing the power integrity analysis for the core power of ASIC. The key approach is to capture the resonant frequency of the complete power delivery network (PDN), including the chip, package and board. From the FFT of the switching activity, the worst case pattern can be obtained by identifying the major frequency content which coincides with the resonance frequency of the PDN. The feasible process flow is demonstrated through an ASIC design. The results illustrate the interaction between the switching activity and the design of chip/package/board.